Rust and FPGAs, is it possible?

Hello to all !

I make this post to ask about the possibility of running Rust code on FPGAs. And if possible, you recommend it ? Or is it in an unstable phase ?

Thank you very much.

Hi, what exactly do you mean with "running Rust code on FPGAs"? Do you want to run Rust on FPGA soft-cores? Do you want to use Rust as hardware description language? Or do you want Rust high level synthesis? In general, you don't tell an FPGA what to run, but rather what to be.

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An interesting idea.

I'm no HDL expert but have managed to get some simple logic working in FPGA from Verilog.

I almost have a working RISC V processor core working written in SpinalHDL. Which is a hardware description language inside Scala.

So the thought did cross my mind if such an HDL could be done in Rust. Basically a Rust to Verilog transpiler, like Spinal or Chisel.

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Ooh, that's an interesting idea. Like what if you could use Rusts type system to represent what was valid HDL somehow and then use a macro to compile that to Verilog or something.


Otherwise, @ManuelCostanzo, if you just wanted to run a Rust program on an FPGA, you could synthesize a RISC-V CPU on your FPGA using something like VexRiscV, which is I think the CPU @ZiCog was referring to, and then compile your Rust code for the RISC-V architecture and run that on your FGPGA CPU.

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Assuming you mean high-level synthesis, there's a recent (January 2020) paper about converting a Rust EDSL into register transfer language.

There's also kaze, another embedded HDL that can generate either Verilog or simulator code.

Another interesting thing is XLS, a Google project that aims to be an intermediate representation generator and optimizer for high-level synthesis, similar to LLVM for CPU code. It might be interesting to try and emit their IR from Rust.

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I have the PicoRV32 implemented on a DE0 Nano FPGA board. https://github.com/cliffordwolf/picorv32

It was a couple of years ago that I spent some time with FPGA, just out of curiosity. Somebody gave me that DE-0 board so I thought I'd take the opportunity see what Verilog was all about. I landed on the PicoRV32 because it is very small and I could easily rip the CPU core out of there and start surrounding it with my own peripherals, memory, UART, GPIO, etc. After all, the idea was to learn some Verilog, not just use some ready made thing.

That led to a happy excursion down the rabbit hole of open source HDL tools, Icarus Verilog http://iverilog.icarus.com/, the Verilator https://www.veripool.org/wiki/verilator, Icestorm http://www.clifford.at/icestorm/, SymbiFlow https://symbiflow.github.io/

The result of all that is here: https://github.com/ZiCog/xoro it runs C code at 100MHz clock. https://github.com/ZiCog/sodor-spinal

The inevitable next step was to create my own RISC V core. I set about creating my own "sodor" corehttps://passlab.github.io/CSE564/notes/lecture08_RISCV_Impl.pdf in SpinalHDL https://spinalhdl.github.io/SpinalDoc-RTD/

The result of that is my "sodor-spinal" core https://github.com/ZiCog/sodor-spinal. Which whilst it decodes and executes RISC V instructions well enough under test does not yet run autonomously.

Recently I was thinking to get my picorv32 running some Rust. But all this is on hold as real work got in the way.

Everyone who complains about the slow compile times of Rust should spend a week with Verilog and the Quartus IDE :slight_smile:

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Slightly off-topic, but HDL tooling is not only slow (I buy that, routing and the like are supposedly NP-complete problems), but generally I find their IDEs outright distasteful. So much complexity hidden behind unnecessarily complicated GUIs, it's not even funny. Never used Quartus, but I've had the bad luck of using some Xilinx tools (the old ISE as well as its revamp, Vivado), and I was not pleased, to say the least.

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Quartus is equally gross. It's huge and slow. The complexity of it's interface is off the scale. The editor is mediocre. Simply compiling ones project take forever, never mind fully synthesizing the design and configuring a device. I find it unusable for riffing on Verilog, the edit/compile turn round time is just too much. I wonder if there is actually anyone out there who uses it as their sole FPGA dev tool.

What finally got me to look into FPGA was the discovery that with Icarus one could create some code and a little test bench and it would simulate and test the design almost instantly. That makes the edit/test development cycle more like working with Python.

Then there is the Verilator Verilog compiler, more difficult to use but very fast, for when you want to simulate something bigger.

I'm looking forward to getting back to FPGA using symbiflow. Which can synthesize a whole RISC V plus ones little extras in seconds.

I can't believe how much you know and how much I can learn. Thank you very much !

I will study everything that was sent

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Don't let me impress you so much. I have only scratched the surface of logic deign and FPGA. Little hobby scale experiments.

Do it give it a go. It's fun.

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it's more of a compiler internal representation, rather than a Rust to FPGA compiler, but LLHD (written in Rust) and Circt (part of the LLVM project) are quite interesting!

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I knew about LLHD, but CIRCT is new to me! Thanks for the link.

I'm actually hoping these efforts eventually lead to languages that can largely supplant Verilog (and VHDL) at least in the hobby space.

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According to the ReadMe of LLHD, it is a part of CIRCT.

I would argue that the closest idea to "Rust on FPGA" would be something like what Xilinx Vitis does: you can write C, C++ or OpenCL code and it gets compiled to hardware definition. Imagine if you could use Rust instead.

I would like to see hardware providers releasing Rust compiler toolchain instead of C compilers for hardware programming in the future. Don't know even if that is possible. Maybe a LLVM based compiler is a barrier for that?

Few years ago people were looking at GPUs for AI. If you're not looking at FPGAs right now, you're missing out.

Related package: GitHub - cogciprocate/ocl: OpenCL for Rust

Related IDE: Vitis Platform

AWS F1: Instâncias F1 do Amazon EC2

I think there already exist some LLVM to FPGA synthesizers (https://llvm.org/devmtg/2014-10/Slides/Baker-CustomHardwareStateMachines.pdf). However to really benefit from the FPGA, one has to understand the HW to make all optimizations. In my opinion this can never be achieved just by synthesizing from any kind of source code (e.g. algorithm transformation for associativity, commutativity, or others like replication, iterative decomposition, pipelining, ...).

However I would really appreciate a Rust-based HDL, which brings in type safety and so on..

You know one of the Big Two HDLs in existence, which all major vendors and open-source tools already support, is a strongly typed full-featured programming language, right?

Yes, but its verification and simulation functionality is rather limited in comparison to (System)Verilog

Yeah, kind of forgot about VHDL.

There is some interesting dynamic between humans and computers, played out through the programming languages they use.

For example Pascal and then Ada were created with the idea of enforcing rules such that programmers would make less mistakes and produce more reliable code. Type safety, array bounds checks and so on. Both of them, despite Ada being mandated by the US military for some time, fell by the way side. I was never sure if that was because programmers rejected those correctness shackles, or if it was because the likes of C and C++ were much more easily available, or for performance reasons or whatever...

VHDL follows in the footsteps of Pascal and Ada with it's anal attention to correctness and verbosity. Characteristics we might think are desirable. Like Ada and Pascal to be overrun by Verilog, which is much more in the free-for-all and be damned mindset of C/C++.

Enter Rust. A much more palatable syntax than Ada. In many ways much more anal about correctness than Ada.

A Rust based HDL begins to sound like a very good idea.

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