Data race allowed array

[anon80458984]

@Cerber-Ursi

If I understand correctly, they mean "as long as access to each u32 is synchronized, I don't care whether access to the whole array is synchronized".

Yeah, sorry for not being clear on this. Formally, let S0, S1, R all be Vec, all of 10^9 elements.

Suppose some writer is trying to change the state from S0 to S1 and some reader reads R.

I require that for all i: R[i] = S0[i] || R[i] = S1[i]. So each u32 has to be the old value or the new value, but the overall R can be partly S0 and partly S1.