I've been going through Concurrency chapter in the Embedded Rust Book and want to be sure I get everything right. The last paragraph says:
All the examples using a critical section (including the
cortex_m::interrupt::Mutex) assume the only other execution thread is the interrupt thread, but on a multi-core system that's no longer true. Instead, we'll need synchronisation primitives designed for multiple cores (also called SMP, for symmetric multi-processing).
These typically use the atomic instructions we saw earlier, since the processing system will ensure that atomicity is maintained over all cores.
Furthermore, in the section on Atomics:
These (atomic) instructions give an alternative to the heavy-handed disabling of all interrupts: we can attempt the increment, it will succeed most of the time, but if it was interrupted it will automatically retry the entire increment operation.
core::sync::atomic::AtomicU64.fetch_or(value, Ordering::AcqRel) as example. For
AArch64 target (Cortex-A72) it gets assembled into something like:
1: ldaxr x8, [x9] orr x10, x8, #<value> stlxr w11, x10, [x9] cbnz w11, 1b
From what I understood, if an interrupt occurs after
LDAXR and interrupt handler modifies the same memory address, it will not dead-lock. But what will happen? Does interrupt routine perform its load-modify-store sequence and then, in the main thread, the whole load-modify-store sequence is retried after returned from the interrupt?