How to pass march flags to cargo?

My cargo project config file in .cargo has the following:

rustflags = [
"-C", "link-arg=-Thifive1-revb-rom.lscript",
"-C", "llvm-args=-align-all-functions=2",
"-C", "debuginfo=2",
"-C", "opt-level=0"
target = "riscv32imac-unknown-none-elf"

Its set to compile for RISC-V rv32imac.

How do I set the march flag as -march=rv32ima in rust config?

Basically, I want all the instructions to be 32bits wide and prevent compiler from compressed (16bits) instructions.

are you looking for --target-feature? if you have a specific CPU model, you can use --target-cpu.

you can ask rusc to show available options, e.g.:

to list supported CPUs for riscv32imac-unknown-none-elf target:

$ rustc --target riscv32imac-unknown-none-elf --print target-cpus
Available CPUs for this target:
    generic-rv32        - This is the default target CPU for the current build target (currently riscv32).

to list supported features:

$ rustc --target riscv32imac-unknown-none-elf --print target-features
Features supported by rustc for this target:
    a                             - 'A' (Atomic Instructions).
    c                             - 'C' (Compressed Instructions).
    d                             - 'D' (Double-Precision Floating-Point).
    e                             - Implements RV32E (provides 16 rather than 32 GPRs).
    f                             - 'F' (Single-Precision Floating-Point).
    m                             - 'M' (Integer Multiplication and Division).
    relax                         - Enable Linker relaxation..
    v                             - 'V' (Vector Extension for Application Processors).
    zba                           - 'Zba' (Address Generation Instructions).
    zbb                           - 'Zbb' (Basic Bit-Manipulation).
    zbc                           - 'Zbc' (Carry-Less Multiplication).
    zbkb                          - 'Zbkb' (Bitmanip instructions for Cryptography).
    zbkc                          - 'Zbkc' (Carry-less multiply instructions for Cryptography).
    zbkx                          - 'Zbkx' (Crossbar permutation instructions).
    zbs                           - 'Zbs' (Single-Bit Instructions).
    zdinx                         - 'Zdinx' (Double in Integer).
    zfh                           - 'Zfh' (Half-Precision Floating-Point).
    zfhmin                        - 'Zfhmin' (Half-Precision Floating-Point Minimal).
    zfinx                         - 'Zfinx' (Float in Integer).
    zhinx                         - 'Zhinx' (Half Float in Integer).
    zhinxmin                      - 'Zhinxmin' (Half Float in Integer Minimal).
    zk                            - 'Zk' (Standard scalar cryptography extension).
    zkn                           - 'Zkn' (NIST Algorithm Suite).
    zknd                          - 'Zknd' (NIST Suite: AES Decryption).
    zkne                          - 'Zkne' (NIST Suite: AES Encryption).
    zknh                          - 'Zknh' (NIST Suite: Hash Function Instructions).
    zkr                           - 'Zkr' (Entropy Source Extension).
    zks                           - 'Zks' (ShangMi Algorithm Suite).
    zksed                         - 'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions).
    zksh                          - 'Zksh' (ShangMi Suite: SM3 Hash Function Instructions).
    zkt                           - 'Zkt' (Data Independent Execution Latency).
    crt-static                    - Enables C Run-time Libraries to be statically linked.

Code-generation features supported by LLVM for this target:
    32bit                         - Implements RV32.
    64bit                         - Implements RV64.
    experimental-zawrs            - 'Zawrs' (Wait on Reservation Set).
    experimental-zca              - 'Zca' (part of the C extension, excluding compressed floating point loads/stores).
    experimental-zcd              - 'Zcd' (Compressed Double-Precision Floating-Point Instructions).
    experimental-zcf              - 'Zcf' (Compressed Single-Precision Floating-Point Instructions).
    experimental-zihintntl        - 'zihintntl' (Non-Temporal Locality Hints).
    experimental-ztso             - 'Ztso' (Memory Model - Total Store Order).
    experimental-zvfh             - 'Zvfh' (Vector Half-Precision Floating-Point).
    forced-atomics                - Assume that lock-free native-width atomics are available.
    h                             - 'H' (Hypervisor).
    lui-addi-fusion               - Enable LUI+ADDI macrofusion.
    no-default-unroll             - Disable default unroll preference..
    no-optimized-zero-stride-load - Hasn't optimized (perform fewer memory operations)zero-stride vector load.
    no-rvc-hints                  - Disable RVC Hint Instructions..
    reserve-x1                    - Reserve X1.
    reserve-x10                   - Reserve X10.
    reserve-x11                   - Reserve X11.
    reserve-x12                   - Reserve X12.
    reserve-x13                   - Reserve X13.
    reserve-x14                   - Reserve X14.
    reserve-x15                   - Reserve X15.
    reserve-x16                   - Reserve X16.
    reserve-x17                   - Reserve X17.
    reserve-x18                   - Reserve X18.
    reserve-x19                   - Reserve X19.
    reserve-x2                    - Reserve X2.
    reserve-x20                   - Reserve X20.
    reserve-x21                   - Reserve X21.
    reserve-x22                   - Reserve X22.
    reserve-x23                   - Reserve X23.
    reserve-x24                   - Reserve X24.
    reserve-x25                   - Reserve X25.
    reserve-x26                   - Reserve X26.
    reserve-x27                   - Reserve X27.
    reserve-x28                   - Reserve X28.
    reserve-x29                   - Reserve X29.
    reserve-x3                    - Reserve X3.
    reserve-x30                   - Reserve X30.
    reserve-x31                   - Reserve X31.
    reserve-x4                    - Reserve X4.
    reserve-x5                    - Reserve X5.
    reserve-x6                    - Reserve X6.
    reserve-x7                    - Reserve X7.
    reserve-x8                    - Reserve X8.
    reserve-x9                    - Reserve X9.
    save-restore                  - Enable save/restore..
    short-forward-branch-opt      - Enable short forward branch optimization.
    sifive7                       - SiFive 7-Series processors.
    svinval                       - 'Svinval' (Fine-Grained Address-Translation Cache Invalidation).
    svnapot                       - 'Svnapot' (NAPOT Translation Contiguity).
    svpbmt                        - 'Svpbmt' (Page-Based Memory Types).
    tagged-globals                - Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits.
    unaligned-scalar-mem          - Has reasonably performant unaligned scalar loads and stores.
    xtheadvdot                    - 'xtheadvdot' (T-Head Vector Extensions for Dot).
    xventanacondops               - 'XVentanaCondOps' (Ventana Conditional Ops).
    zicbom                        - 'Zicbom' (Cache-Block Management Instructions).
    zicbop                        - 'Zicbop' (Cache-Block Prefetch Instructions).
    zicboz                        - 'Zicboz' (Cache-Block Zero Instructions).
    zihintpause                   - 'zihintpause' (Pause Hint).
    zmmul                         - 'Zmmul' (Integer Multiplication).
    zve32f                        - 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension).
    zve32x                        - 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW).
    zve64d                        - 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension).
    zve64f                        - 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension).
    zve64x                        - 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW).
    zvl1024b                      - 'Zvl' (Minimum Vector Length) 1024.
    zvl128b                       - 'Zvl' (Minimum Vector Length) 128.
    zvl16384b                     - 'Zvl' (Minimum Vector Length) 16384.
    zvl2048b                      - 'Zvl' (Minimum Vector Length) 2048.
    zvl256b                       - 'Zvl' (Minimum Vector Length) 256.
    zvl32768b                     - 'Zvl' (Minimum Vector Length) 32768.
    zvl32b                        - 'Zvl' (Minimum Vector Length) 32.
    zvl4096b                      - 'Zvl' (Minimum Vector Length) 4096.
    zvl512b                       - 'Zvl' (Minimum Vector Length) 512.
    zvl64b                        - 'Zvl' (Minimum Vector Length) 64.
    zvl65536b                     - 'Zvl' (Minimum Vector Length) 65536.
    zvl8192b                      - 'Zvl' (Minimum Vector Length) 8192.

Use +feature to enable a feature, or -feature to disable it.
For example, rustc -C target-cpu=mycpu -C target-feature=+feature1,-feature2

Code-generation features cannot be used in cfg or #[target_feature],
and may be renamed or removed in a future version of LLVM or rustc.

march is used by clang, the C/C++ compiler based on LLVM, not by rustc.

As pointed out above, you can disable compressed instructions by adding the following to rustflags:

 "-C", "target-feature=-c",

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