Embedded Rust: How to configure interrupt on an STM32F103 MCU

Embedded
5

I used this link by mjepronk and I trimmed down my code to the following which works:

// std and main are not available for bare metal software
#![no_std]
#![no_main]

extern crate panic_halt;

use cortex_m_rt;
use stm32f1;

use cortex_m_semihosting::hprintln;

use cortex_m_rt::entry;
use stm32f1::stm32f103;
use stm32f1::stm32f103::interrupt;

/* Code Description
- Power on LED on PC13 on PB12 rising edge interrupt
- Power off LED on PC13 on PB12 falling edge interrupt
*/

#[interrupt]
fn EXTI1() -> ! {
    hprintln!("Interrupt!!!").unwrap();
    // let peripherals = stm32f103::Peripherals::take().unwrap();
    // peripherals.EXTI.pr.write(|w| w.pr1().set_bit());
}

// use `main` as the entry point of this application
#[entry]
fn main() -> ! {
    // enable the GPIO clock for IO port C
    let mut core_peripherals = stm32f103::CorePeripherals::take().unwrap();
    core_peripherals.NVIC.enable(stm32f103::Interrupt::EXTI1);
    // get handles to the hardware
    let peripherals = stm32f103::Peripherals::take().unwrap();
    // PC13 output 50 MHz
    peripherals.RCC.apb2enr.write(|w| w.iopcen().set_bit());
    peripherals.GPIOC.crh.write(|w| unsafe {
        w.mode13().bits(0b11);
        w.cnf13().bits(0b00)
    });
    // PA1 input
    peripherals.RCC.apb2enr.write(|w| w.iopaen().set_bit());
    peripherals.GPIOA.crl.write(|w| unsafe {
        w.mode1().bits(0b00);
        w.cnf1().bits(0b10)
    });
    // pull-up
    peripherals.GPIOA.bsrr.write(|w| w.br1().set_bit());
    // set MR12 in IMR
    peripherals.EXTI.imr.write(|w| w.mr1().set_bit());
    // set MR12 in RTMR
    peripherals.EXTI.rtsr.write(|w| w.tr1().set_bit());

    loop {
        match peripherals.GPIOA.idr.read().idr1() {
            stm32f103::gpioa::idr::IDR0R::HIGH => {
                let _res = hprintln!("A1 = HIGH");
            }
            stm32f103::gpioa::idr::IDR0R::LOW => {
                let _res = hprintln!("A1 = LOW");
            }
        };
        cortex_m::asm::delay(2000000);
    }
}

However, if I change the above to PB12, as in

// std and main are not available for bare metal software
#![no_std]
#![no_main]

extern crate panic_halt;

use cortex_m_rt;
use stm32f1;

use cortex_m_semihosting::hprintln;

use cortex_m_rt::entry;
use stm32f1::stm32f103;
use stm32f1::stm32f103::interrupt;

/* Code Description
- Power on LED on PC13 on PB12 rising edge interrupt
- Power off LED on PC13 on PB12 falling edge interrupt
*/

#[interrupt]
fn EXTI0() -> ! {
    hprintln!("Interrupt!!!").unwrap();
    // let peripherals = stm32f103::Peripherals::take().unwrap();
    // peripherals.EXTI.pr.write(|w| w.pr1().set_bit());
}

#[interrupt]
fn EXTI1() -> ! {
    hprintln!("Interrupt!!!").unwrap();
    // let peripherals = stm32f103::Peripherals::take().unwrap();
    // peripherals.EXTI.pr.write(|w| w.pr1().set_bit());
}

#[interrupt]
fn EXTI2() -> ! {
    hprintln!("Interrupt!!!").unwrap();
    // let peripherals = stm32f103::Peripherals::take().unwrap();
    // peripherals.EXTI.pr.write(|w| w.pr1().set_bit());
}

#[interrupt]
fn EXTI3() -> ! {
    hprintln!("Interrupt!!!").unwrap();
    // let peripherals = stm32f103::Peripherals::take().unwrap();
    // peripherals.EXTI.pr.write(|w| w.pr1().set_bit());
}

#[interrupt]
fn EXTI4() -> ! {
    hprintln!("Interrupt!!!").unwrap();
    // let peripherals = stm32f103::Peripherals::take().unwrap();
    // peripherals.EXTI.pr.write(|w| w.pr1().set_bit());
}

// use `main` as the entry point of this application
#[entry]
fn main() -> ! {
    // enable the GPIO clock for IO port C
    let mut core_peripherals = stm32f103::CorePeripherals::take().unwrap();
    core_peripherals.NVIC.enable(stm32f103::Interrupt::EXTI0);
    core_peripherals.NVIC.enable(stm32f103::Interrupt::EXTI1);
    core_peripherals.NVIC.enable(stm32f103::Interrupt::EXTI2);
    core_peripherals.NVIC.enable(stm32f103::Interrupt::EXTI3);
    core_peripherals.NVIC.enable(stm32f103::Interrupt::EXTI4);
    // get handles to the hardware
    let peripherals = stm32f103::Peripherals::take().unwrap();
    // PC13 output 50 MHz
    peripherals.RCC.apb2enr.write(|w| w.iopcen().set_bit());
    peripherals.GPIOC.crh.write(|w| unsafe {
        w.mode13().bits(0b00);
        w.cnf13().bits(0b10)
    });
    // PB12 input
    peripherals.RCC.apb2enr.write(|w| w.iopben().set_bit());
    peripherals.GPIOB.crh.write(|w| unsafe {
        w.mode12().bits(0b11);
        w.cnf12().bits(0b00)
    });
    // pull-up
    peripherals.GPIOB.bsrr.write(|w| w.br12().set_bit());
    // set MR12 in IMR
    peripherals.EXTI.imr.write(|w| w.mr12().set_bit());
    // set MR12 in RTMR
    peripherals.EXTI.rtsr.write(|w| w.tr12().set_bit());

    loop {
        match peripherals.GPIOB.idr.read().idr12() {
            stm32f103::gpioa::idr::IDR0R::HIGH => {
                let _res = hprintln!("PB12 = HIGH");
            }
            stm32f103::gpioa::idr::IDR0R::LOW => {
                let _res = hprintln!("PB12 = LOW");
            }
        };
        cortex_m::asm::delay(2000000);
    }
}

it does not work. This is weird because I expect the configuration process for both pins to be the same . :confused: