Yes, Miri's running confirmed this.
After t1 execution with Release ordering on READY, READY is now true, and DATA is 123. All other threads that access these two variables will observe the latest writes/updates.
The DATA is not atomic nor mutex, and two threads-- t2, t3--can now access it at the same time. Accessing the DATA by t2 and t3 exactly at the same is unlikely here as number of threads is too low, but it is likely when number of threads is many. Don't you think it is a race as two threads race to access it?
As afetisov comment mentioned that simple load of aligned data type are atomic on most CPU architecture so above mentioned race(if it is indeed race) is okay.